1. Field of the Invention
The present invention relates generally to switches and electronic communication. More specifically, the present invention relates to switching between multiple hosts and multiple synthetic or logical devices in an intelligent PCIe switch.
2. Description of the Related Art
Non-transparent bridging first appeared in the late 1990's in the form of the DEC (Digital Equipment Corp.) “Drawbridge”, later marketed by Intel Corp as the 21555 Bridge. Non-transparent bridging on PCI Express is described in several articles authored by technical staff at PLX Technology of Sunnyvale, Calif. (See “Using Non-transparent Bridging in PCI Express Systems” by Jack Regula, 2004; “Non-Transparent Bridging Makes PCI-Express HA Friendly,” by Akber Kazmi, EE Times, Aug. 14, 2003, the contents of each which is hereby incorporated by reference).
Computer architectures have advanced greatly over the years. Lately, it is becoming more and more commonplace for chip designers to include external data interfaces, such as Universal Serial Bus (USB) interface controllers into their motherboards. These interfaces are known as host controllers. The processor is typically then connected to the other components of the computer system via an input/output (I/O) interconnect system.
There are many different computer I/O interconnect standards available. One of the most popular over the years has been the peripheral component interconnect (PCI) standard. PCI allows the bus to act like a bridge, which isolates a local processor bus from the peripherals, allowing a Central Processing Unit (CPU) of the computer to connect to a host of IO devices through this interconnect.
Recently, a successor to PCI has been popularized, termed PCI Express (or, simply, PCIe). PCIe provides higher performance, increased flexibility and scalability for next-generation systems, while maintaining software compatibility with existing PCI applications. Compared to legacy PCI, the PCI Express protocol is considerably more complex, with three layers—the transaction, data link and physical layers.
In a PCI Express system, a root complex device connects the processor and memory subsystem to the PCI Express switch fabric comprised of one or more switch devices (embodiments are also possible without switches, however). In PCI Express, a point-to-point architecture is used. Similar to a host bridge in a PCI system, the root complex generates transaction requests on behalf of the processor, which is interconnected through a local I/O interconnect. Root complex functionality may be implemented as a discrete device, or may be integrated with the processor. A root complex may contain more than one PCI Express port and multiple switch devices can be connected to ports on the root complex or cascaded.
As an example, FIG. 1 is a block diagram depicting a normal shared I/O architecture having a standard PCIe switch 102 controlled by management host 104 running switch management software. Switch 102 services one or more hosts, shown as connected host 106 and connected host 108 (also referred to as “local hosts”), for example servers, PCs, and other computing devices. Also connected to switch are one or more devices 110-116 that typically provide some type of function or service for the connected hosts. Within switch 102 are virtual devices 118-124. Virtual devices 118 and 120 are connected to connected host 106 and virtual devices 122 and 124 are connected to connected host 108. Some of these virtual devices have data paths to physical devices 110-114. The functionality and roles of virtual devices 118-124 are described in U.S. Pat. No. 8,521,941, entitled “MULTI-ROOT SHARING OF SINGLE-ROOT INPUT/OUTPUT VIRTUALIZATION,” issued on Aug. 27, 2013, which is incorporated by reference for all purposes, where a solution was described that used resource redirection methods when multiple hosts are connected using the non-transparent ports of a PCIe switch that supports shared I/O mechanisms.